As the semiconductor industry has progressed into nanometer technology nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a vertical gate all around (VGAA) transistor. A typical VGAA transistor enables enhanced control of the charge carriers along the lengthwise direction through a complete encirclement of the channel region of a semiconductor nanowire by a gate dielectric and a gate electrode. The VGAA transistor has a reduced short channel effect (e.g. compared to a planar transistor), because the channel region may be surrounded by the gate electrode so that an effect of the source/drain region on an electric field of the channel region may be reduced (e.g. relative to a planar transistor). On the other hand, a subthreshold drain current of a field effect transistor (FET) is the current that flows between the source and drain of the FET when the transistor is in a subthreshold region (where the gate-to-source voltage is below the threshold voltage). A steep subthreshold slope of the FET may improve the on and off current ratio, and therefore reduces a leakage current.